Welcome to ipCorePackager’s documentation!¶
Readme File¶
IP-Core packager is a tool which generates component.xml or _hw.tcl files which are description of interface of hardware design usually written in Verilog or VHDL. Result is the package with HDL (Verilog/VHDL) files, constraints files (XDC, UCF, …) tcl based GUI and package description file. IP-Core packages greatly simplifies integration of hardware projects, all major synthesis tools (Xilinx Vivado, Intel Quartus, …) are supporting them directly and for rest it is better to have IP-Core because of consystency.
- ipCorePackager package
- Submodules
- ipCorePackager.busInterface module
- ipCorePackager.component module
- ipCorePackager.constants module
- ipCorePackager.helpers module
- ipCorePackager.intfIpMeta module
- ipCorePackager.model module
- ipCorePackager.otherXmlObjs module
- ipCorePackager.packager module
- ipCorePackager.port module
- ipCorePackager.tclGuiBuilder module
- ipCorePackager.type module
- ipCorePackager.uniqList module