Welcome to ipCorePackager's documentation!
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Readme File
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IP-Core packager is a tool which generates component.xml or _hw.tcl files which are description of interface of hardware design usually written in Verilog or VHDL. Result is the package with HDL (Verilog/VHDL) files, constraints files (XDC, UCF, ...) tcl based GUI and package description file. IP-Core packages greatly simplifies integration of hardware projects, all major synthesis tools (Xilinx Vivado, Intel Quartus, ...) are supporting them directly and for rest it is better to have IP-Core because of consystency.

.. toctree::
   :maxdepth: 3
   :caption: Contents:

   ipCorePackager



Indices and tables
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* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`